This invention relates generally to the use of semiconductor substrates and more specifically to an improved method of fabricating a substrate having regions of varying height.
Semiconductor wafers can be formed in many shapes for a variety of uses. One important practical application for semiconductor substrates is in the fabrication of micro-electro-mechanical systems (MEMS) in the form of electrostatic actuators. In such devices and in other applications, it may be useful to have regions of the semiconductor with varying heights. Design flexibility is significantly increased by the ability to shape the semiconductor wafer. For example, when a fabricated silicon wafer is used as the substrate of an electrostatic actuator the electric field force can vary substantially due to the shape of the substrate.
Using current semiconductor fabrication processes, it is difficult to form a substrate having regions of varying height. Typically a semiconductor wafer, for example a silicon wafer, is fabricated through a process that includes deposition, masking, and etching. Deposition may include depositing a protective layer on top of the silicon substrate. The protective layer may be, for example, silicon dioxide, silicon nitride, a polymer, or other like material. The protective layer may be deposited or may be formed upon the substrate.
Masking includes placing a pattern upon the protective layer in a stencil-like fashion. The wafer is then selectively etched through an etching process that may be, for example, a reactive ion etching process or a wet chemical etching process, or some other etching process known in the art. The selective etching of the silicon wafer creates a structure as determined by the pattern as described above.
Typically the wafer is etched straight down. This process limits the design flexibility in terms of the shape of the fabricated wafer. That is, the three-dimensional structure created is a projection of the pattern. Typically, fabrication of wafers is done as a batch process. This allows a thousand, or more, devices to be fabricated at a time from a single large wafer. Throughout the process there is no physical machining of the wafer surface, no tools touch the wafer. It is not practical to address each device on the wafer, instead the entire wafer is subjected to the process described above. The sequence of operations of the process must be tailored to produce the desired device shape.
Using the method as described above it is difficult to vary the size of portions of the wafer. Methods such as undercutting or inverting the wafer provide a limited ability to vary the height of portions of the substrate, thus providing only minimal increase in design flexibility.
A method is disclosed for creating a subsurface patterned layer and exposing the subsurface patterned layer to further processing. A first protective layer is formed upon a first substrate layer. The first protective layer is then selectively patterned such that patterned portions of the first protective layer are reduced. A second substrate layer is then bonded to the first protective layer such that a subsurface patterned layer is formed. A second protective layer is formed upon the second substrate layer and the second protective layer is then selectively patterned such that portions of the second substrate layer are exposed. The exposed portions of the second substrate layer are then etched such that the subsurface patterned layer is exposed.
Other features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description, that follows below.